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cy7c10612dv33 16-mbit (1 m 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-49315 rev. *c revised october 18, 2011 16-mbit (1 m 16) static ram features high speed ? t aa = 10 ns low active power ? i cc = 175 ma at 100 mhz low cmos standby power ? i sb2 = 25 ma operating voltages of 3.3 0.3 v 2.0 v data retention automatic power-down when deselected ttl compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free 54-pin tsop ii package functional description the cy7c10612dv33 is a high performance cmos static ram organized as 1,048,576 words by 16 bits. to write to the device, take chip enables (ce ) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enables (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see truth table on page 10 for a complete description of read and write modes. the input or output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low and we low). the cy7c10612dv33 is available in a 54-pin tsop ii package with center power and ground (revolutionary) pinout. 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 1m x 16 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 i/o 0 ? i/o 7 oe i/o 8 ? i/o 15 ce we ble bhe a 9 a 19 logic block diagram [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 2 of 14 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 4 thermal resistance .......................................................... 4 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 5 data retention waveform ................................................ 5 ac switching characteristics ......................................... 6 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc solutions ......................................................... 14 [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 3 of 14 selection guide description - 10 unit maximum access time 10 ns maximum operating current 175 ma maximum cmos standby current 25 ma pin configuration figure 1. 54-pin tsop ii (top view) [1] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 i/o 11 18 17 20 19 23 28 25 24 22 21 27 26 v ss i/o 10 i/o 12 v cc i/o 13 i/o 14 v ss a 16 a 17 a 11 a 12 a 13 a 14 i/o 0 a 15 i/o 7 i/o 9 v cc i/o 8 i/o 15 a 19 a 4 a 3 a 2 a 1 ce v cc we nc ble nc v ss oe a 8 a 7 a 6 a 5 a 0 nc a 9 bhe a 10 10 a 18 46 45 47 50 49 48 51 54 53 52 i/o 2 i/o 1 i/o 3 v ss v cc v ss i/o 6 i/o 5 v cc i/o 4 note 1. nc pins are not connected on the die. [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 4 of 14 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [2] ...............................?0.5 v to +4.6 v dc voltage applied to outputs in high z state [2] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................ ?0.5 v to v cc + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage (mil-std-883, method 3015) ..... ............................> 2001 v latch up current ................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 3.3 v ? 0.3 v dc electrical characteristics over the operating range parameter description test conditions - 10 unit min max v oh output high voltage min v cc , i oh = ?4.0 ma 2.4 ? v v ol output low voltage min v cc , i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd ? v in ? v cc ?1 +1 ? a i oz output leakage current gnd ? v out ? v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc, i out = 0 ma, cmos levels ?175ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce ? v ih , v in ? v ih or v in ? v il , f = f max ?30ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce ? v cc ? 0.3 v, v in ? v cc ? 0.3 v, or v in ? 0.3 v, f = 0 ?25ma capacitance parameter [3] description test conditions 54-pin tsop ii unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 6 pf c out i/o capacitance 8pf thermal resistance parameter [3] description test conditions 54-pin tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 24.18 ? c/w ? jc thermal resistance (junction to case) 5.40 ? c/w note 2. v il(min) = ?2.0 v and v ih(max) = v cc + 2 v for pulse durations of less than 20 ns. 3. tested initially and after any design or proces s changes that may affect these parameters. [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 5 of 14 ac test loads and waveforms figure 2. ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 5 pf* including jig and scope (b) r1 317 ? r2 351 ? rise time: fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5 v 30 pf* * capacitive load consists of all components of the test environment high z characteristics: (a) > 1 v/ns data retention characteristics over the operating range parameter description conditions min typ [5] max unit v dr v cc for data retention 2 ? ? v i ccdr data retention current v cc = 2 v, ce ? v cc ? 0.2 v, v in ? v cc ? 0.2 v or v in ? 0.2 v ??25ma t cdr [6] chip deselect to data retention time 0 ? ? ns t r [7] operation recovery time t rc ??ns data retention waveform figure 3. data retention waveform 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc notes 4. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0 v). 100 ? s (t power ) after reaching the minimum operating v dd , normal sram operation begins including reduction in v dd to the data retention (v ccdr , 2.0 v) voltage. 5. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 6. tested initially and after any design or proce ss changes that may affect these parameters. 7. full device operation requires linear v cc ramp from v dr to v cc(min.) ? 50 ? s or stable at v cc(min.) ? 50 ? s. [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 6 of 14 ac switching characteristics over the operating range parameter [4] description - 10 unit min max read cycle t power v cc (typical) to the first access [5] 100 ? ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z 1 ? ns t hzoe oe high to high z [6] ?5ns t lzce ce low to low z [6] 3?ns t hzce ce high to high z [6] ?5ns t pu ce low to power-up [7] 0?ns t pd ce high to power-down [7] ?10ns t dbe byte enable to data valid ? 5 ns t lzbe byte enable to low z 1 ? ns t hzbe byte disable to high z ? 5 ns write cycle [8, 9] t wc write cycle time 10 ? ns t sce ce low to write end 7 ? ns t aw address setup to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 7?ns t sd data setup to write end 5.5 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [6] 3?ns t hzwe we low to high z [6] ?5ns t bw byte enable to end of write 7 ? ns notes 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, and input pulse levels of 0 to 3.0 v. test conditions for the read cycle use output loading shown in part a) of figure 2 on page 5 , unless specified otherwise. 5. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 6. t hzoe , t hzce , t hzwe , t hzbe , t lzoe , t lzce , t lzwe , and t lzbe are specified with a load capacitance of 5 pf as in (b) of figure 2 on page 5 . transition is measured ? 200 mv from steady state voltage. 7. these parameters are guaranteed by design and are not tested. 8. the internal write time of the memory is defined by the overlap of we , ce = v il . chip enable must be active and we and byte enables must be low to initiate a write, and the transition of any of these signals can terminate. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 9. the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 7 of 14 switching waveforms figure 4. read cycle no. 1 (address transition controlled) [10, 11] figure 5. read cycle no. 2 (oe controlled) [11, 12] previous data valid data out valid rc t aa t oha t rc address data i/o 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data i/o v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb notes 10. the device is continuously selected. oe , ce = v il , bhe , ble or both = v il . 11. we is high for read cycle. 12. address valid before or similar to ce transition low. [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 8 of 14 figure 6. write cycle no. 1 (ce controlled) [13, 14] figure 7. write cycle no. 2 (we controlled, oe low) [13, 14] switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data i/o address ce we bhe , ble data in valid t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data i/o address ce we bhe ,ble data in valid notes 13. data i/o is high impedance if oe , bhe , and/or ble = v ih . 14. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 9 of 14 figure 8. write cycle no. 3 (ble or bhe controlled) [15] switching waveforms (continued) t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble ce we data in valid note 15. data i/o is high impedance if oe , bhe , and/or ble = v ih . [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 10 of 14 ordering code definitions truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c10612dv33-10zsxi 51-85160 54-pin tsop ii (pb-free) industrial temperature grade: i = industrial pb-free package type: zs = 54-pin tsop ii speed grade: 10 ns voltage range: 3 v to 3.6 v process technology: c9, 90 nm single chip enable bus width = 16 density = 16-mbit fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress cy 10 zs 7 c 1 06 x 1 i - v33 2 d [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 11 of 14 package diagrams figure 9. 54-pin tsop type ii (22.4 11.84 1.0 mm) z54-ii package outline, 51-85160 51-85160 *c [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 12 of 14 acronyms document conventions units of measure table 1. acronyms used in this document acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package ttl transistor-transistor logic we write enable table 2. units of measure symbol unit of measure c degree celsius mhz megahertz a microampere ? s microsecond ma milliampere mm millimeter mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt [+] feedback
cy7c10612dv33 document number: 001-49315 rev. *c page 13 of 14 document history page document title: cy7c10612dv33, 16-mbit (1 m 16) static ram document number: 001-49315 rev. ecn no. orig. of change submission date description of change ** 2589743 vkn / pyrs 10/15/08 new datasheet *a 2718906 vkn 06/15/09 post to external web *b 3128718 pras 01/05/11 template updates. style changes. io changed to i/o through out the document. under data retention characteristics on page 6, ?typ? is associated with a new footnote # 10. included ordering code definitions, acro nyms and units of measure tables. updated package diagram from ** to *a. *c 3412972 tava 10/18/2011 updated features . updated dc electrical characteristics . updated switching waveforms . updated package diagrams . updated in new template. [+] feedback
document number: 001-49315 rev. *c revised october 18, 2011 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c10612dv33 ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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